Voltage controlled delay circuits (VCDC) are widely used in numerous applications such as ring oscillators, delay lock loops, and so on. A particular application of interest is a voltage controlled ring oscillator having a plurality of stages of VCDC configured in a ring topology, wherein each one of said stages of VCDC receives an input from a preceding stage and outputs an output to a succeeding stage, and a circuit delay from the input to the output is controlled by a control voltage. FIG. 1 depicts a 3-stage voltage controlled ring oscillator 100 comprising three VCDC 110, 120, and 130; each VCDC, configured in a differential circuit topology, has a first (or positive) input terminal Vi+, a second (or negative) input terminal Vi−, a first (or positive) output terminal Vo+, a second (or negative) output terminal Vo−, and a control terminal VC; an input is defined as a voltage difference between the two input terminals V+ and Vi−; an output is defined as a voltage difference between the two output terminals Vo+ and Vo−; and a circuit delay from the input to the output is controlled by a control voltage applied at the control terminal VC. A control voltage VCTL is applied to all three VCDC 110-130; the control voltage VCTL determines the circuit delay of the three VCDC, and therefore determines an oscillation frequency of the ring oscillator.
There are many circuits suitable for embodying voltage controlled delay circuits. A circuit of particular interest is a CML (current-mode logic) amplifier 200 shown in FIG. 2. CML amplifier 200 comprises: a current source 210 comprising an NMOS (n-type metal-oxide semiconductor) transistor 211, a differential pair 220 comprising NMOS transistors 221 and 222, and a load 230 comprising resistors 231 and 232. Here, VDD is a power supply node. CML amplifier 200 is well known in prior art and self-explanatory to those of ordinary skills in the art, therefore no detailed explanation is given here. A higher voltage at the VC terminal leads to a larger bias current Ib, resulting in a shorter circuit delay of the delay circuit, and consequently a higher oscillation frequency of the ring oscillator. There is a drawback in CML amplifier 200, however, that a common mode voltage of the output depends on the bias current Ib; therefore, when the control voltage changes, the common mode voltage of the output also changes. In many applications, it is highly desirable that the common mode voltage remains substantially the same in spite of a change in the control voltage.
What is desired is a voltage controlled delay circuit that has an output of a substantially fixed common mode voltage when the control voltage changes.